1. Field of the Invention
The present invention relates to a semiconductor device of a chip size package (hereinafter called “CSP: Chip Size (Scale) Package”) structure.
This application is counterparts of Japanese patent application, Ser. No. 169010/2003, filed Jun. 13, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
With a demand for a reduction in the size of electronic equipment, miniaturization and densification of a semiconductor device have been made in recent years. Therefore, a semiconductor device of a CSP structure has been proposed wherein the shape of the semiconductor device is brought closer to a semiconductor element (chip) to reduce its size.
The semiconductor device of the CSP structure needs to enhance the array density of external connecting terminals. Therefore, bump terminals (hereinafter called “bump electrodes”) are used which are electrically connected to their corresponding connecting pads as the external connecting terminals and extend vertically from a chip surface.
A general structure of this type of semiconductor device is shown in FIG. 5. In the same drawing, reference numeral 501 indicates a semiconductor substrate formed with an integrated circuit, reference numeral 502 indicates a electrode pad, reference numeral 503 indicates a passivation film, reference numeral 504 indicates an insulating film having an electrical insulating property similar to the passivation film 503, reference numeral 506 indicates a bump electrode, reference numeral 505 indicates a wiring between the electrode pad 502 and the bump electrode 506, reference numeral 507 indicates an encapsulating resin layer, and reference numeral 508 indicates an external terminal made up of solder for connection to the outside.
As a material for the insulating film 504, for example, polyimide relatively high in elasticity is used to relax stress applied to the external terminal 508 and the bump electrode 506 and prevent the occurrence of cracks in a semiconductor integrated circuit containing the passivation film 503 and the electrode pad 502. The thickness of the insulating film ranges from approximately 0.005 to 0.01 mm.
In order to reduce stress applied to the electrode pad 502, such layout design that the bump electrode 506 is formed at a position where it does not overlap an opening (corresponding to a portion in which the insulating film 504 located directly above the electrode pad 502 does not exist) defined in the insulating film 504 when viewed from above is performed. The size of the opening defined in the insulating film 504 ranges from approximately 0.02 to 0.06 mm in diameter, and the size of the bump electrode 506 ranges from approximately 0.15 to 0.4 mm in diameter. This type of semiconductor device has been described in, for example, a patent document 1 (Japanese Laid Open Patent Application No. 2002-93945).
However, there may be cases in which when the area of a chip for an integrated circuit is small or electrode pads provided on the chip are large in number, it becomes difficult to locate the position to form the bump electrode 506 sufficiently away from the opening of the insulating film 504 as shown in FIG. 5, and hence the bump electrode 506 is formed at a position where it overlaps the opening of the insulating film 504. In such a case, there is a large possibility that large stress is applied to each electrode pad so that a crack will occur in the electrode pad. Thus a problem arose in that the reliability of the semiconductor device was deteriorated.